A low power logarithmic A/D converter

Author

Francesconi, F. ; Maloberti, F.

Author_Institution

Dipartimento di Elettronica, Pavia Univ., Italy

Volume

1

fYear

1996

fDate

12-15 May 1996

Firstpage

473

Abstract

The architecture of a new logarithmic analog-to-digital converter employing a successive approximation algorithm is presented. We used a mixed capacitor-array, resistor-string structure for the logarithmic conversion. The converter was derived from its linear counterpart by modifying of the conversion algorithm. Computer simulations show that the proposed approach is suitable to design high quality audio converters in low power low voltage applications. A prototype of the converter has been implemented in a 1.6 μm single poly double metal CMOS technology

Keywords

CMOS integrated circuits; Hi-Fi equipment; analogue-digital conversion; 1.6 micron; Si; analog-to-digital converter; capacitor-array; high quality audio converters; logarithmic A/D converter; low power LV applications; low power logarithmic ADC; mixed structure; resistor-string structure; single poly double metal CMOS technology; successive approximation algorithm; CMOS technology; Computer architecture; Computer simulation; Digital signal processing; Dynamic range; Electronic mail; Energy consumption; Low voltage; Signal processing algorithms; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.539987

Filename

539987