Title :
Stochastic decoding for LDPC convolutional codes
Author :
Lee, Xin-Ru ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.
Keywords :
convolutional codes; decoding; parity check codes; stochastic processes; LDPC convolutional codes; LDPC-CC decoder; decoder architecture; log-BP decoder; sliding window; stochastic decoding; storage reduction; time-varying LDPC-CC; virtual edge compensation; Algorithm design and analysis; Convolutional codes; Decoding; Logic gates; Parity check codes; Program processors; Registers; LDPC convolutional codes; stochastic decoding;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271843