Analysis of non-idealities in folding and interpolating ADCs using a behavioral model approach

Author

Varma, Sumir ; Suyama, Ken ; Gopinathan, Venugopa

Author_Institution

Dept. of Electr. Eng., Columbia Univ., New York, NY, USA

Volume

1

fYear

1996

fDate

12-15 May 1996

Firstpage

508

Abstract

This paper presents a behavioral model approach for analyzing a folding and interpolating analog-to-digital converter (ADC). The model is constructed using mathematical equations in a C program to describe the behavior of each block of the system, and it is used to analyze non-idealities such as mismatches, bandwidth limitations, and non-linearity in the folding amplifiers, interpolation network, and comparators of the folding and interpolating ADC. The results aid the design of a folding and interpolating ADC by providing a comprehensive set of design criteria that must be satisfied by each building block

Keywords

analogue-digital conversion; circuit analysis computing; comparators (circuits); interpolation; synchronisation; A/D convertor; C program; analog-to-digital converter; bandwidth limitations; behavioral model approach; bit synchronisation; comparator nonlinearity; design criteria; folding amplifier nonlinearity; folding/interpolating ADCs; interpolation network nonlinearity; mismatches; nonidealities analysis; Bandwidth; Circuits; Interpolation; Laboratories; Mathematical model; Microelectronics; Nonlinear equations; Performance analysis; Power system modeling; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.539996

Filename

539996