Two-level configuration for FPGA: A new design methodology based on a computing fabric

Large FPGAs require more and more time and expertise to efficiently target custom applications. This paper presents a new methodology based on two configuration levels. At the lowest level, the architecture is fully synthesized, placed and routed by experts to implement a 2-D mesh architecture of configurable algorithmic token machines. At the highest level, the users can program those machines to implement custom processing and routing. The architecture is data driven. The operations are triggered by the arrival of operands, leading to a large and functional pipeline spread over the whole FPGA. This methodology enables the fast implementation of data processing algorithms by people who are not experts in FPGA design, while achieving higher performances than a pure software solution. Two simple examples (FIR and FFT) illustrate the proposed methodology and demonstrate how it is possible to benefit from the expertise encapsulated at low level by just configuring the high level. Another advantage of the proposed methodology is the opportunity to dynamically reconfigure the fabric very quickly to best match the computation requirements at run time.