A static technique for high-speed CMOS state machine design

Author

McLaughlin, Kevin ; Schwab, Andrew J. ; Aylor, James H.

Author_Institution

Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

108

Lastpage

111

Abstract

This paper presents a technique for designing CMOS high-speed state machines with a clock frequency ranging from DC to greater than 130 MHz in 1.2-μm technology. This technique applies weak feedback to known high-speed dynamic circuits to achieve both static and high-speed capability. Two-phase nonoverlapping clocking is used to eliminate any possible races. Propagation delays of critical paths are minimized by performing their logic functions within the master stage of the flip-flops

Keywords

CMOS logic circuits; circuit feedback; finite state machines; flip-flops; logic design; sequential circuits; synchronisation; timing; 1.2 micron; 130 MHz; CMOS state machine design; flip-flops; high-speed CMOS; high-speed dynamic circuits; static technique; two-phase nonoverlapping clocking; weak feedback; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Feedback circuits; Flip-flops; Frequency; Inverters; Latches; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404598

Filename

404598

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3020396