DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation

Author

Siozios, K. ; Koutroumpezis, G. ; Tatas, K. ; Soudris, D. ; Thanailakis, A.

Author_Institution

Dept. Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

fYear

2005

fDate

04-08 April 2005

Abstract

A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the Graphical User Interface.

Keywords

field programmable gate arrays; logic CAD; reconfigurable architectures; FPGA; bitstream compression; bitstream encryption; bitstream generation; bitstream reallocation; dynamic-reconfiguration; graphical user interface; memory management; partial-reconfiguration; read-back technique; run-time-reconfiguration; software tool implementation; Cryptography; Design automation; Field programmable gate arrays; Hardware; Logic functions; Memory management; Runtime; Software algorithms; Software tools; Very large scale integration; FPGA; bitstream generator; partial; reconfiguration; runtime; tool development;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International

Print_ISBN

0-7695-2312-9

Type

conf

DOI

10.1109/IPDPS.2005.158

Filename

1420032