DocumentCode
3020625
Title
Refinements of Rent´s rule allowing accurate interconnect complexity modeling
Author
Verplaetse, Peter
Author_Institution
Dept. of Electron. & Inf. Syst., Ghent Univ., Belgium
fYear
2001
fDate
2001
Firstpage
251
Lastpage
252
Abstract
The complexity of the interconnect topology of a circuit is well captured by Rent´s rule. This rule can be applied for a priori wire-length estimation, which is useful for improving the quality of generated layouts, and could be used for reducing the number of design iterations. It can also successfully be applied for the generation of synthetic benchmark circuits. However Rent´s role is an empirical approximation, and there are many deviations. This paper describes possible extensions to Rent´s rule and discusses some of its applications
Keywords
VLSI; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; Rent rule; VLSI design; integrated circuit layout; interconnect complexity model; synthetic benchmark circuit; wire length; Application software; Circuit topology; Clocks; Delay; Design automation; Information systems; Integrated circuit interconnections; Statistical distributions; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2001 International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-1025-6
Type
conf
DOI
10.1109/ISQED.2001.915235
Filename
915235
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