An NProd Algorithm IP Design for Real-Time Image Matching Application onto FPGA

Real-time image matching is usually a core operation in many embedded applications. Often in such applications, low implementation costs and short time-to-market are required. Field programmable gates array (FPGA) based reconfigurable hardware implementation, which provides all the benefits of hardware acceleration while retaining the flexibility of programmability, presents an effective approach to real-time image processing applications. In view of the Verilog HDL and FPGA programmable technology, an efficient FPGA-based intellectual property (IP) core designing methodology to implement such high performance algorithm as normalized product correlation (NProd) image matching algorithm is discussed in this paper, which includes IP-core implementing flow, parametric RTL-level software IP-core design, hardware synthesis, simulation and verification.