DocumentCode
3020682
Title
RC power bus maximum voltage drop in digital VLSI circuits
Author
Bai, G. ; Bobba, S. ; Hajj, I.N.
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear
2001
fDate
2001
Firstpage
257
Lastpage
258
Abstract
This paper presents an input-independent method for finding bounds on the voltage drop in RC power bus in digital VLSI circuits. The voltage at power bus nodes is expressed in term of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous HL and LH switching in a clock subinterval. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes
Keywords
RC circuits; VLSI; circuit optimisation; digital integrated circuits; power supply circuits; sensitivity analysis; system buses; timing; HL switching; LH switching; RC power bus; digital VLSI circuit; logic circuit; maximum voltage drop; optimization; sensitivity analysis; timing analysis; Circuits; Clocks; Frequency; Laplace equations; Power systems; Sensitivity analysis; Timing; Uncertainty; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2001 International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-1025-6
Type
conf
DOI
10.1109/ISQED.2001.915238
Filename
915238
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