• DocumentCode
    3020695
  • Title

    Output-dependent delay cancellation technique for high-accuracy current-steering DACs

  • Author

    Long Cheng ; Yu-Jing Lin ; Fan Ye ; Ning Li ; Jun-yan Ren

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2012
  • fDate
    20-23 May 2012
  • Firstpage
    2729
  • Lastpage
    2732
  • Abstract
    In this paper, an output-dependent delay cancellation (ODDC) technique is proposed. For a high-accuracy digital-to-analog converter (DAC), the delay differences caused by output voltage is one of the major nonlinearities that deteriorate the dynamic performance. The ODDC technique has the advantages of significant improvement on the dynamic performance in a wide frequency range without increasing the noise floor. ODDC can eliminate the switching time variations caused by output voltage of DAC through tuning the bulk voltage of switches in the deep N-well. The algorithm of ODDC technique is derived. To verify the implementation, a 14 bits 400MS/s current-steering DAC with ODDC is simulated and the SFDR can be improved by about 12dB with proper circuit parameters.
  • Keywords
    delays; digital-analogue conversion; ODDC technique; SFDR; circuit parameter; deep N-well; digital-to-analog converter; high-accuracy current-steering DAC; output-dependent delay cancellation technique; switch voltage; switching time variation elimination; word length 14 bit; Delay; Floors; Impedance; Noise; Switches; Threshold voltage; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
  • Conference_Location
    Seoul
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-0218-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2012.6271872
  • Filename
    6271872