The decomposition of long FFT´s for high throughput implementation

One of the major limiting factors in high throughput FFT systems implementation is the bus bandwidth. The data traffic over the bus consists of 3 types: input/output data, exponential coefficients (W factors) and instruction code (for the executing processor). Reduction of the bus load requires employment of a dedicated processor with internal memory and LUT (for the W factors) that will be able to compute certain sized FFT modules. Computation of larger sized FFT´s using these smaller sized modules then requires support by an external LUT. Minimization of this LUT size and the bus load effect of the twiddle factor introduction can be achieved through full exploitation of the nature of the W factors behavior in the FFT passes. The decomposition of the large FFT into smaller modules for this purpose is explored and a high throughput system (up to 2.2MHz for FFT´s of up to 16K points) implementation based on this approach, with the Zoran ZR34161 Vector Signal Processor is presented.