DocumentCode
3020824
Title
An effective current source cell model for VDSM delay calculation
Author
Korshak, Alexander ; Lee, Jyh-Chwen
Author_Institution
Avant Corp., Fremont, CA, USA
fYear
2001
fDate
2001
Firstpage
296
Lastpage
300
Abstract
We present a new approach to model delay of the digital cell in very deep submicron (VDSM) IC designs. It provides higher accuracy for both delay and transition time than the conventional effective capacitance approximation. The cell is modeled by an effective current source that emulate the behavior of the transistor network. The proposed model is based upon the standard timing tables of the characterized cell
Keywords
VLSI; delay estimation; digital integrated circuits; integrated circuit modelling; VDSM delay calculation; current source cell model; digital cell; standard timing tables; transistor network behaviour emulation; transition time; very deep submicron IC designs; Capacitance; Capacitors; Delay effects; Delay estimation; Digital integrated circuits; Equations; Integrated circuit modeling; Propagation delay; Timing; Utility programs;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2001 International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-1025-6
Type
conf
DOI
10.1109/ISQED.2001.915246
Filename
915246
Link To Document