Buffer-architecture exploration for routers in a hierarchical network-on-chip

This paper explores efficient buffer architectures for top-level mesh routers in HiNoC, a hierarchical network-on-chip. Multiple approaches to buffering are discussed and a size-performance comparison of synthesis results is performed. Among the possible buffer architectures, output buffering and middle buffering are examined carefully by evaluating the impact of variations in significant parameters on the router´s overall area. This is done by synthesizing a generic design onto a FPGA. Eventually, middle buffering is identified as best buffer architecture and the influence of the aforementioned parameters on the area requirements is formalized.