Power grid modeling technique for hierarchical power network analysis

Author

Zhu, Ning ; Koh, Han Young

fYear

2001

fDate

2001

Firstpage

313

Lastpage

318

Abstract

This paper presents a novel power grid modeling technique that can be used in hierarchical power network analysis of multi-million gate designs. The RC network of the power grid of a macro block is extracted and reduced by an AWE-based algorithm. The resulting model replaces the macro blocks during the top level power network analysis, this greatly reduces both memory and CPU time usage. Our experiments show that more than 90% of R´s and C´s in the original power network can be reduced with less than 10% loss in accuracy. Furthermore, the CPU time required for the power network analysis of full-chip designs is reduced by 10 to 100 times

Keywords

RC circuits; application specific integrated circuits; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; AWE-based algorithm; CPU time; RC network; full-chip designs; hierarchical power network analysis; multi-million gate designs; power grid modeling technique; top level power network analysis; Circuit simulation; Clocks; Current density; Data mining; Frequency; Integrated circuit interconnections; Performance analysis; Power grids; Presence network agents; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2001 International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1025-6

Type

conf

DOI

10.1109/ISQED.2001.915249

Filename

915249