Title :
On fault-tolerant FFT butterfly network design
Author :
Lu, Shyue-Kung ; Wu, Cheng-Wen ; Kuo, Sy-Yen
Author_Institution :
Dept. of Electr. Eng., Loong Hua Inst., Taipei, Taiwan
Abstract :
We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively
Keywords :
VLSI; digital signal processing chips; fast Fourier transforms; fault tolerant computing; integrated circuit reliability; FFT butterfly network design; FFT processors; VLSI; bit-level design; fault-tolerant methods; module-level design; reconfiguration algorithm; Discrete Fourier transforms; Equations; Fast Fourier transforms; Fault tolerance; Hardware; Logic arrays;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.540354
