A fully qualified analog design flow for nonvolatile memories technologies

Author

Daglio, P. ; Araldi, M. ; Morbarigazzi, M. ; Roma, C.

Author_Institution

STMicroelectron. N.V., Milan, Italy

fYear

2001

fDate

2001

Firstpage

451

Lastpage

455

Abstract

The wide range and rapid increase in the complexity of CAD tools demands proven and safe design flows. This paper presents a fully validated methodology integrated as analog design flow to design nonvolatile memories. Specifically, it has been applied to designs in 0.35 mm EEPROM and 0.13 um flash memory processes developed in the company. The remarkable feature of the proposed methodology is the excellent integration between CAD tools released by different vendors and internally developed solutions. Furthermore we show a flow which provides full compatibility and flexibility among analog design steps that could cut down time-to-design, time-to-market and streamline the design quality, thus enhancing the circuit yield and robustness

Keywords

analogue circuits; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit yield; integrated memory circuits; 0.13 micron; 0.35 micron; CAD tools; EEPROM; circuit yield; compatibility; design flows; design quality; flash memory processes; flexibility; fully qualified analog design flow; nonvolatile memories; robustness; time-to-design; time-to-market; Circuit simulation; Circuit testing; Design automation; Design optimization; EPROM; Flash memory; Inductors; Oscillators; Phase noise; Resonance;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2001 International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1025-6

Type

conf

DOI

10.1109/ISQED.2001.915270

Filename

915270