Title :
Chip-level substrate noise analysis with network reduction by fundamental matrix computation
Author :
Murasaka, Yoshitaka ; Nagata, Makoto ; Ohmoto, Takafumi ; Morie, Takashi ; Iwata, Atsushi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
Abstract :
The fundamental matrix (F-matrix) based substrate mesh reduction technique is incorporated in a chip-level substrate noise simulation methodology. A system-level equivalent circuit model of a 0.6 μm CMOS substrate noise evaluation chip demonstrates simulation errors of less than 15% by comparing it with 100 ps 100 μV substrate noise waveform measurements
Keywords :
CMOS integrated circuits; equivalent circuits; integrated circuit modelling; integrated circuit noise; matrix algebra; substrates; 0.6 micron; CMOS substrate noise evaluation chip; chip-level substrate noise analysis; chip-level substrate noise simulation methodology; fundamental matrix computation; matrix-based substrate mesh reduction technique; network reduction; simulation errors; substrate noise waveform measurements; system-level equivalent circuit model; Analytical models; Circuit noise; Circuit simulation; Computer networks; Equivalent circuits; Noise generators; Noise measurement; Noise reduction; Semiconductor device modeling; Voltage;
Conference_Titel :
Quality Electronic Design, 2001 International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1025-6
DOI :
10.1109/ISQED.2001.915275
