A strategy for avoiding pipeline interlock delays in a microprocessor

Author

Yoshida, Toyohiko ; Matsuo, Masahito ; Ueda, Tatsuya ; Saito, Yuichi

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

fYear

1990

fDate

17-19 Sep 1990

Firstpage

14

Lastpage

19

Abstract

Pipelining of instruction execution significantly improves computer performance, but high dependencies between instructions limit the maximum concurrency that is achievable by pipelining. A hardware scheme to avoid pipeline interlock delays caused by dependencies in address generation is proposed. This scheme is implemented in the 32-b microprocessor M32/100. The M32/100 has a hardware interlock mechanism with scoreboard registers and a working stack pointer that is modified prior to the execution of each instruction. A simulator has been written and several benchmarks have been executed to investigate the performance achieved by these schemes

Keywords

computer architecture; microprocessor chips; pipeline processing; program compilers; scheduling; 32 bit; M32/100; address generation; benchmarks; computer performance; concurrency; dependencies; hardware interlock mechanism; instruction execution; microprocessor; pipeline interlock delays; pipelining; scoreboard registers; simulator; working stack pointer; Clocks; Decoding; Delay; Hardware; Large scale integration; Logic; Microprocessors; Pipeline processing; Registers; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130148

Filename

130148