Title :
Sorted QR decomposition for high-speed MMSE MIMO detection based wireless communication systems
Author :
Miyaoka, Yuya ; Nagao, Yuhei ; Kurosaki, Masayuki ; Ochi, Hiroshi
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Fukuoka, Japan
Abstract :
In this paper, we propose a hardware architecture of high-speed sorted QR decomposition for a 4×4 MMSE-MIMO decoder. A QR decomposition (QRD) is commonly used in many MIMO detection algorithms. In particular, a sorted QR decomposition (SQRD) is a advanced algorithm to improve a MIMO detection performance. The proposed architecture can decompose an augmented channel matrix for MMSE detection by using modified Gram-Schmidt algorithm with pipelining and resource sharing processing. This architecture can be applied in a high-throughput MIMO-OFDM system such as IEEE802.11n which supports data throughput of up to 600Mbps. We implement the proposed architecture with 334k gates in 90nm CMOS technology. The proposed design can achieve a high performance of up to 50.0 million 4×4 SQRD operations per second with the maximum operating frequency of 300 MHz.
Keywords :
CMOS integrated circuits; MIMO communication; OFDM modulation; decoding; mean square error methods; resource allocation; wireless channels; CMOS technology; Gram-Schmidt algorithm; IEEE802.11n; MIMO detection algorithm; MIMO detection performance; MMSE-MIMO decoder; SQRD; augmented channel matrix; data throughput; hardware architecture; high-speed MMSE MIMO detection; high-speed sorted QR decomposition; high-throughput MIMO-OFDM system; pipelining processing; resource sharing processing; size 90 nm; wireless communication system; Logic gates; MIMO; Read only memory; Receivers; Silicon carbide;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271909