Improved code optimization method utilizing memory addressing operation and its application to DSP compiler

Improved methods to derive an efficient memory access pattern for DSPs, of which memory is accessed only by address registers (ARs), are discussed. In this article, variables in a program and AR operations are modeled by a novel access graph. The number of possible AR operations between two memory accesses are used as one of the weights for every edge. After removal of appropriate cycles and forks in a given graph with taking weights on edges, an efficient memory allocation is decided. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for μPD77230, and resultant memory allocations for several examples are very much improved