A 1-V 1.1-MHz BW digitally assisted multi-bit multi-rate hybrid CT ΣΔ with 78-dB SFDR

A second-order multi-bit hybrid continuous-time (CT) ΣΔ modulator has been implemented in a 65-nm CMOS technology. The circuit ensures jitter immunity granted by the use of multi-rate switched-capacitor (SC) DACs. An auxiliary digital assistance technique reduces integrators output swing. The modulator provides 10.8 bits of resolution over a signal bandwidth of 1.1 MHz and a spurious free dynamic range (SFDR) of 78 dB. The chip draws 1.1 mW from a 1-V supply.