High level synthesis in DSP ASIC optimization

Author

Isoaho, Jouni ; Öberg, Johnny ; Hemani, Ahmed ; Tenhunen, Hannu

Author_Institution

Signal Process. Lab., Tampere Univ. of Technol., Finland

fYear

1994

fDate

19-23 Sep 1994

Firstpage

75

Lastpage

78

Abstract

In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

Keywords

FIR filters; application specific integrated circuits; circuit optimisation; digital filters; digital signal processing chips; high level synthesis; DSP ASIC optimization; Matlab; SYNT synthesis tools; Synopsys synthesis tools; behavioural VHDL description; coefficient optimization; digital signal processing; high level synthesis; multiply-accumulate based FIR filters; power-of-two FIR filters; rule based preallocator; Application specific integrated circuits; Design optimization; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; High level synthesis; Logic; Process design; Quantization; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404605

Filename

404605