High-speed VLSI implementation of FIR lattice filters

The benefits and costs of using merged arithmetic in the design of FIR lattice filters are investigated. The first design presented reduces hardware over the conventional lattice filter by combining the multiply and add operation into one block. The second design achieves a significant speed-up by deferring the carry-propagating addition until after the final lattice filter stage. This speed-up incurs a slight cost in additional hardware and additional wire communication between the lattice filter stages.