Approaches to digital compensation of excess loop delay in continuous-time Delta-Sigma modulators using a scaled quantizer

In this paper, two new approaches to the digital compensation of excess loop delay in continuous-time Delta-Sigma modulators are presented. They are based on a shifting of the transfer characteristic of a scaled flash ADC used for the implementation of the quantizer. The first approach considers an adaptation of the reference voltage of the comparators while the second approach focuses on the implementation of additional comparators. Both approaches are verified by means of simulations performed on a Verilog-A model of a third-order continuous-time Delta-Sigma modulator while replacing the corresponding quantizers by means of transistor-level implementations.