DocumentCode :
3022617
Title :
Structure exploration in high-level language description for logic synthesis
Author :
Chen, Yulin ; Ku, Tsuwei ; Chia, Wei Kong ; Chiu, Scott ; Lam, Ophelia
Author_Institution :
Hitachi Micro Systems, San Jose, CA, USA
fYear :
1994
fDate :
19-23 Sep 1994
Firstpage :
63
Lastpage :
66
Abstract :
This paper presents a new idea in handling the information flow between high-level RTL description and logic synthesis besides the logic functionality. The objective of this approach is to optimally synthesize a circuit by dynamically changing the logic synthesis script based on the high-level description implication,The technique used here is to explore the degree of the regularity which is more visible in high-level language description than in low level logic design and circuit structure. This degree of tie regularity will trigger different logic synthesis script dynamically. The experimental results show that this approach can save as much as 30% total area than using single synthesis script in several real design cases
Keywords :
high level synthesis; integrated circuit design; logic design; high-level RTL description; high-level language description; logic CAD; logic synthesis; regularity degree; structure exploration; Circuit synthesis; Design methodology; Equations; Hardware design languages; High level languages; Logic circuits; Logic design; Logic functions; Multiplexing; Signal analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
Type :
conf
DOI :
10.1109/ASIC.1994.404608
Filename :
404608
Link To Document :
بازگشت