Structure exploration in high-level language description for logic synthesis

This paper presents a new idea in handling the information flow between high-level RTL description and logic synthesis besides the logic functionality. The objective of this approach is to optimally synthesize a circuit by dynamically changing the logic synthesis script based on the high-level description implication,The technique used here is to explore the degree of the regularity which is more visible in high-level language description than in low level logic design and circuit structure. This degree of tie regularity will trigger different logic synthesis script dynamically. The experimental results show that this approach can save as much as 30% total area than using single synthesis script in several real design cases