Title :
Design strategies for the final adder in a parallel multiplier
Author :
Stelling, Paul F. ; Oklobdzija, Vojin
Author_Institution :
Dept. of Comput. Sci., California Univ., Davis, CA, USA
fDate :
Oct. 30 1995-Nov. 1 1995
Abstract :
In this paper we address the problem of adding two n-bit numbers when the bit arrival times are arbitrary (but known in advance). In particular we address a simplified version of the problem where the input arrival times for the i/sup th/ significant bits of both addends are the same, and the arrival times t/sub i/ have a profile of the form: t/sub 0//spl les/t/sub 1//spl les/.../spl les/t/sub k/=t/sub k+1/=...=t/sub p/>t/sub p+1//spl ges/.../spl ges/t/sub n-1/. This profile is important because it matches the signal arrival time profile of the reduced partial products in a parallel multiplier before they are summed in the final adder. In this paper we present a design strategy specific to arrival time profiles generated by partial product reduction trees constructed by optimal application of the Three Dimensional Method presented by V.G. Oklobdzija et al. (1995). This strategy can be used to obtain adders for any arrival time profile that matches the above form, as well as a broad class of arrival time profiles where even greater variation in the input times is allowed. Finally, we show that our designs significantly outperform the standard adder designs for the uniform signal arrival profile, yielding faster adders that (for these profiles) are also simpler and use fewer gates.
Keywords :
VLSI; adders; carry logic; circuit optimisation; delays; digital arithmetic; logic CAD; multiplying circuits; parallel architectures; signal flow graphs; I/O delay modelling; VLSI circuits; XOR delays; arbitrary bit arrival times; carry-select blocks; carry-skip blocks; complex hybrid structure; delay optimisation; final adder design strategies; optimal adders; parallel multiplier; partial product reduction trees; reduced partial products; ripple-carry blocks; signal arrival profile; signal arrival time profile; three dimensional method; Adders; Circuits; Computer science; Delay; Joining processes; Time division multiplexing; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7370-2
DOI :
10.1109/ACSSC.1995.540616