High speed Dual Mode Logic Carry Look Ahead Adder

Author

Levi, Itamar ; Bass, O. ; Kaizerman, A. ; Belenky, Alexander ; Fish, Alexander

Author_Institution

VLSI Syst. Center, Ben-Gurion Univ. of the Negev, Beer-Sheva, Israel

fYear

2012

fDate

20-23 May 2012

Firstpage

3037

Lastpage

3040

Abstract

A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

Keywords

adders; carry logic; high-speed integrated circuits; logic design; logic gates; low-power electronics; CLA delay; DML gates; critical paths; dynamic mode; dynamic switching; high speed dual mode logic carry look ahead adder; input vectors; low power TSMC process; low power dissipation; power consumption; size 40 nm; static mode; word length 32 bit; Adders; CMOS integrated circuits; Delay; Logic gates; Power dissipation; Topology; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6271959

Filename

6271959