Low-power LDPC decoding based on iteration prediction

Low-density parity-check (LDPC) codes have very broad applications. Low-power LDPC decoder design is becoming increasingly important for wireless and other power-constraint systems. Compared to disabling or simplifying the decoder circuit, reducing the power supply voltage can bring more power reduction. Through predicting the number of iterations needed for convergence, this paper proposes to make full use of the time available for decoding and scale down the power supply voltage in the remaining decoding iterations. Novel iteration prediction schemes are developed. The proposed schemes require very small hardware overhead and do not lead to noticeable error-correcting performance loss. Compared to using the original supply voltage and powering off the decoder after convergence, the proposed schemes can bring 50% dynamic power reduction for an example LDPC code, and the power saving further increases with the signal-to-noise ratio.