A low-complexity high-throughput ASIC for the SC-FDMA MIMO detectors

A novel low-complexity detection scheme is proposed for the multiple-input multiple-output (MIMO) single-carrier frequency division-multiple access (SC-FDMA) systems, which is suitable for ASIC implementations. The proposed detection scheme makes an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) frequency domain equalizer (FDE) detector and finds symbols with higher error probability among them and browse more candidates for them in the constellation to improve their initial estimate. Based on this approach, architecture is introduced that achieves superior bit error rate (BER) performance compared to the conventional MMSE FDE. The performance of the proposed design is close to the existing maximum likelihood-post detection processing (ML-PDP) scheme, while achieving a significantly lower complexity , i.e., 450× less Euclidean distance (ED) calculations in 16-QAM. The ASIC implementation of the proposed architecture, the first ASIC for SC-FDMA detectors to-date, achieves a 3× higher throughput than the best design reported to-date.