Title :
A two´s complement pipeline multiplier
Author :
Cheng, Edmund K. ; Mead, Carver A.
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two´s complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.
Keywords :
Circuits; Clocks; Delay; Digital arithmetic; Digital signal processing; Laboratories; Pipelines; Propulsion; Signal design; Signal processing algorithms;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '76.
DOI :
10.1109/ICASSP.1976.1169990
