DocumentCode
3023064
Title
Fault tolerance in RNS: an efficient approach
Author
Radhakrishnan, Damu ; Pyon, Taejin
Author_Institution
Dept. of Electr. Eng., Idaho Univ., Moscow, ID, USA
fYear
1990
fDate
17-19 Sep 1990
Firstpage
41
Lastpage
44
Abstract
Minimization of the error-correction hardware for single fault tolerance in residue number systems (RNSs) is proposed. A novel approach for the design of an error calculator for single fault tolerance in RNS arithmetic is presented. It corrects the error concurrently during normal operation. Furthermore, the computation of each error is achieved in-parallel by a number of smaller look-up tables. This allows a considerable reduction in the total error calculator hardware
Keywords
digital arithmetic; error correction; fault tolerant computing; number theory; RNS arithmetic; concurrent error correction; error calculator; error-correction hardware; look-up tables; minimisation; residue number systems; single fault tolerance; Arithmetic; Circuit faults; Concurrent computing; Electrical fault detection; Error correction; Fault tolerance; Fault tolerant systems; Hardware; Parallel processing; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2079-X
Type
conf
DOI
10.1109/ICCD.1990.130156
Filename
130156
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