A CMOS low voltage high performance interface

Author

Trotter, J.D. ; Rekhi, S. ; Chava, V. ; Kale, P.C.

Author_Institution

Microsyst. Prototyping Lab., Mississippi State Univ., MS, USA

fYear

1994

fDate

19-23 Sep 1994

Firstpage

44

Lastpage

48

Abstract

Low voltage CMOS interface circuitry with self-correcting pull-up and pull-down output resistances to match the printed circuit board transmission line impedance, suitable for use in both series and parallel high-speed digital communication between integrated circuits and suitable for interfacing CMOS to heterogeneous logic (e.g. ECL), is described. The output driver impedance is controlled by the use of a pull-up and a pull-down, binary weighted transistor ladder in conjunction with an A-to-D convertor and an external resistor, representing the transmission line impedance

Keywords

CMOS logic circuits; analogue-digital conversion; comparators (circuits); digital communication; driver circuits; A-to-D convertor; binary weighted transistor ladder; external resistor; heterogeneous logic; high-speed digital communication; low voltage CMOS interface circuitry; output driver impedance; printed circuit board transmission line impedance; self-correcting pull-down output resistances; self-correcting pull-up output resistances; CMOS digital integrated circuits; CMOS integrated circuits; CMOS logic circuits; Digital communication; Distributed parameter circuits; Driver circuits; High speed integrated circuits; Impedance matching; Low voltage; Printed circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404612

Filename

404612