DocumentCode
3023599
Title
A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC
Author
Ritter, Rudolf ; Kauffman, John G. ; Ortmanns, Maurits
Author_Institution
Inst. of Microelectron., Univ. of Ulm, Ulm, Germany
fYear
2012
fDate
20-23 May 2012
Firstpage
3138
Lastpage
3141
Abstract
This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No digital correction is needed because linearity of the 2-step-flash ADC is provided by a capacitor-array matching and CDS prevents missing codes due to offset in the MDAC.
Keywords
amplifiers; analogue-digital conversion; capacitors; digital-analogue conversion; sample and hold circuits; capacitor-array matching; correlated double sampling; high speed 2-step-flash analog-to-digital converters; multiplying digital-to-analog converter; power efficient MDAC design; residue amplification; sample-and-hold amplifier; Ash; Capacitors; Clocks; Delay; Frequency response; Resistance; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6271987
Filename
6271987
Link To Document