A compact resistorless 1.5-V CMOS current reference with 16.5-ppm/°C temperature coefficient

In this paper a novel temperature compensated current reference with modified PMOS cascode architecture is presented. Using PMOS transistors and substituting the typical current source resistor with a diode connected NMOS transistor, better temperature compensation is achieved avoiding the use of large valued resistors. This architecture, designed in the IBM 0.18 μm CMOS 7RF SOI technology, achieves a 16.5 ppm/°C temperature coefficient over range of 20 °C to 130 °C together with reduced power consumption, 38.7 μW at 1.5 V, and silicon area, 130μm².