Title :
A high-resolution Time-to-Digital Converter based on parallel delay elements
Author :
Yao, Chen ; Jonsson, Fredrik ; Chen, Jian ; Zheng, Li-Rong
Author_Institution :
Dept. of Inf. & Commun. Technol., R. Inst. of Technol., Stockholm, Sweden
Abstract :
This paper presents a flash-type Time to Digital Converter (TDC) based on parallel delay elements in 65-nm CMOS process technology. By using parallel delay elements the conversion resolution of the TDC becomes equal to the difference of delay elements rather than the delay time of each element. A Sensed Amplifier Flip Flop (SAFF) ensures narrow sampling window. Operating at 1.2-V supply, this TDC shows 3ps resolution with 0.5LSB of INL and 0.33LSB of DNL respectively and consumes average power 442μW.
Keywords :
CMOS integrated circuits; amplifiers; delay circuits; flip-flops; sensors; time-digital conversion; CMOS process technology; SAFF; conversion resolution; flash-type TDC; flash-type time-to-digital converter; narrow sampling window; parallel delay element; power 442 muW; sensed amplifier flip flop; size 65 nm; time 3 ps; time delay; voltage 1.2 V; Clocks; Delay; Layout; Noise; Power demand; Signal resolution; Transistors;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271992
