DocumentCode :
3023781
Title :
Figures of merit for system path time estimation
Author :
Hsi, C.G. ; Tucker, S.G.
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
fYear :
1990
fDate :
17-19 Sep 1990
Firstpage :
49
Lastpage :
55
Abstract :
A model to help in the evaluation of various technologies for large systems is presented. The space modeled is considered to be made up of a number of VLSI chips sufficient to comprise a CPU and cache arranged on a single planar package. The inputs consist of technology constraints and system design parameters. From these, a number of design characteristics are computed based on formulas derived from relationships observed in previous generations of large systems, and a system path-time figure of merit is then calculated. With some additional simplifying assumptions, several technology figures of merit can be derived. These include a measure of circuit density in circuits/ns2, a generalized power-delay-cooling figure of merit, and a technology figure of merit involving the ratio of circuit delay to circuits/ns2. The relationship of these to several existing chip and package technology figures of merit is also discussed
Keywords :
VLSI; circuit reliability; packaging; CPU; VLSI chips; cache; circuit delay; circuit density; figure of merit; planar package; power-delay-cooling; system path time estimation; Central Processing Unit; Cooling; Delay; Logic arrays; Logic circuits; Logic design; Magneto electrical resistivity imaging technique; Packaging; Power system modeling; Space technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
Type :
conf
DOI :
10.1109/ICCD.1990.130159
Filename :
130159
Link To Document :
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