A 25 Gb/s full-rate CDR circuit based on quadrature phase generation in data path

This paper presents a 25 Gb/s clock and data recovery circuit using a full-rate clock and quadrature data phases. An adaptive slicer is used in the system front-end to equalize the distorted data to minimize duty-cycle distortion due to inter-symbol interference. The proposed structure uses an open-loop phase averaging block in the data path to generate the required quadrature phases for phase detection using a mixer. A receiver chip that uses an external clock and is based on the proposed technique is designed and laid out in a 90-nm CMOS process. The chip occupies 0.846 mm² and based on post-layout simulation results, it consumes 107 mW from a 1.2 V supply.