A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping

This paper presents a two-stage second-order noise shaping time-to-digital converter (TDC) using a one-bit digitally-controlled oscillator (DCO). The clocks output from DCOs are counted and digitized as in a conventional gated ring oscillator (GRO) TDC. A time error is propagated to the second DCO, which provides second-order noise shaping. In the conventional GROTDC, internal oscillators must maintain their phase state. However, because of the leak current, the stored phase states are degraded or even lost. In our proposed architecture, the DCOs always oscillate and need not maintain their phase state. Therefore, our proposed TDC is more suitable in leaky recent process than a GROTDC is. Because no switched capacitor or opamp is used, the proposed TDC can be implemented in a small area and with low power. Mismatches in the oscillation frequency between the DCOs might occur. However, error detection and correction can be performed using a first-order least mean square (LMS) filter. In a standard 65-nm CMOS process, an SNDR of 51 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 65 MHz, where the power is 271 μW.