Modeling the Flip-Chip Wetting Process

A numerical model is presented for the portion of the flip-chip joining process where liquid-state solder bumps on the substrate and on the device merge (wet) to form full interconnections. An excellent agreement is demonstrated between calculations and experimental data for the accompanying reduction as a function of time in the device-substrate gap height resulting from the wetting process. The model is based on the detailed description of the random wetting transition of every interconnection in large devices, parametrized by a single parameter describing the wetting dynamics of the solder (including, for instance, the retarding effect of oxidation). This allows the model to be used to systematically study the effect of a number of variables (thermal expansion and heating rates, substrate warpage, spatial distribution of solder bump volumes on the substrate and device, etc.) on the rate of occurrence of important defects that appear during the flip-chip wetting process, such as electrical open (nonwet) or short (bridge) defects.