Title :
Design for routability of a high-density gate array
Author :
Harberts, Dick W. ; Van den Elshout, Dré A J M ; Veendrick, Harry J.M.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The factors that determine the routability of high-density gate array (HDGA) logic designs are analyzed. The base array, leaf cells, and placement and routing software are optimized for routability. Design for routability reduces chip area, cost, and turnaround time. The surface areas of experimental designs are less than those of conventional standard-cell designs with similar performance. The base array, leaf cells, and placement and routing software are optimized for routability. An HDGA version of a 10×10-b fully-pipelined multiplier is designed both in a three-metal layer technology and a technology with two metal layers and straps. The resulting HDGA implementations are equal in area and show very similar performance to a SC version with two metal layers
Keywords :
logic CAD; logic arrays; SC version; base array; chip area; cost; design for routability; fully-pipelined multiplier; high-density gate array; leaf cells; logic designs; placement software; routing software; straps; surface areas; three-metal layer technology; turnaround time; CMOS logic circuits; Complexity theory; Computer architecture; Costs; Integrated circuit interconnections; Laboratories; Logic arrays; Logic design; Routing; Wires;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130160
