Title :
Precise exceptions in asynchronous processors
Author :
Manohar, Rajit ; Nyström, Mika ; Martin, Alain J.
Author_Institution :
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
Abstract :
The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous processors that does not block the instruction fetch when exceptions do not occur; the cost of the exception handling mechanism is only encountered when an exception occurs during execution - an infrequent event
Keywords :
asynchronous sequential logic; exception handling; instruction sets; microprocessor chips; pipeline processing; asynchronous processors; exception handling mechanism; implementation strategy; instruction fetch; precise exceptions; processor architectures; software complexity; Algorithms; Computer architecture; Computer science; Costs; Floating-point arithmetic; Hardware; Laboratories; Modems; Operating systems; Software performance;
Conference_Titel :
Advanced Research in VLSI, 2001. ARVLSI 2001. Proceedings. 2001 Conference on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1038-8
DOI :
10.1109/ARVLSI.2001.915547
