A low-power asynchronous VLSI FIR filter

An asynchronous FIR filter, based on a single bit-plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coefficient-set. The proposed architecture has the property that coefficients in a sign-magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs