A high-performance input access scheme for ATM multicast switching

This paper proposes an input access scheme for input-queued ATM multicast switches achieving high system throughput, low packet delay, and low packet loss probability. In the scheme, multicast and unicast packets of each input port are separately queued and all multicast queues take priority over the unicast queues. In addition, all multicast or unicast queues are fairly served by means of the cyclic-priority access discipline. In particular, each unicast queue is handled on a windowed-service basis, and each multicast packet is switched in a one-shot scheduling manner. To evaluate the performance of the access scheme, we employ an approximate queueing model of an N×N generic multicast switch with finite buffer size at each input port possessing Bernoulli multicast and unicast arrivals. We also show simulation results to demonstrate the accuracy of the analysis and the superiority of the scheme over existing schemes with respect to system throughput, packet delay, and packet loss probability