Title :
Width-adaptive data word architectures
Author_Institution :
Dept. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA
Abstract :
We discuss number representations for width-adaptive data word architectures. The number representations are self-delimiting, permitting asynchronous implementations with dynamic width adaptivity and reduced energy-complexity. We describe how these architectures can be realized with asynchronous VLSI techniques, and show that they exhibit better energy and throughput characteristics than traditional asynchronous implementations. We study some of the tradeoffs in the design of this class of architectures
Keywords :
VLSI; adders; asynchronous circuits; integrated circuit design; logic CAD; logic simulation; asynchronous VLSI techniques; asynchronous implementations; dynamic width adaptivity; energy characteristics; number representations; reduced energy-complexity; self-delimiting; throughput characteristics; width-adaptive data word architectures; Adders; Algorithm design and analysis; Circuit simulation; Computer architecture; Delay; Energy efficiency; Laboratories; Power engineering and energy; Throughput; Very large scale integration;
Conference_Titel :
Advanced Research in VLSI, 2001. ARVLSI 2001. Proceedings. 2001 Conference on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1038-8
DOI :
10.1109/ARVLSI.2001.915555
