Title :
Logic gates dynamic modeling by means of an ultra-compact MOS model
Author :
Consoli, Elio ; Giustolisi, Gianluca ; Palumbo, Gaetano
Author_Institution :
DIEEI - (Dipt. di Ing. Elettr. Elettron. e Inf.), Univ. degli Studi di Catania, Catania, Italy
Abstract :
In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates.
Keywords :
CMOS digital integrated circuits; invertors; logic design; logic gates; nanotechnology; CMOS inverter; logic gates dynamic modeling; propagation delay; stacked-transistor gates; ultra-compact I-V nanometer MOS model; ultra-compact MOS model; CMOS integrated circuits; Capacitance; Delay; Integrated circuit modeling; Inverters; Logic gates; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6272018
