A novel methodology for power delivery network optimization in 3-D ICs using through-silicon-via technology

Three-dimensional integrated circuits (3-D IC) are available through the die-stacking and through-silicon-via (TSV) technologies. The 3-D IC using the TSV brings the performance improvement through the minimization of wire length and footprint area. However, the 3-D ICs have many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D ICs. The power delivery network in 3-D IC with flip chip package is largely composed of power/ground (P/G) bumps and P/G TSVs. Because the number of P/G bumps is limited and the size of P/G TSV is larger than that of standard cell, it is important to optimize the P/G bumps and P/G TSVs together while satisfying the IR-drop constraint. In this paper, we investigated an effect of the number of power bumps and power TSVs on the IR-drop in 3-D IC floorplan level and proposed the methodology that reduces the number of power bumps by 88.25% on average while the number of power TSVs and maximum IR-drop are comparable to the previous methodology.