Improved hard-decision decoding LDPC Codec IP design

Author

Kim, Daehyun ; Chung, Biwoong ; Kim, Roy E.

Author_Institution

Samsung Electron. Co., Ltd., Hwaseong, South Korea

fYear

2012

fDate

20-23 May 2012

Firstpage

416

Lastpage

419

Abstract

This paper presents an area efficient low density parity check (LDPC) encoder/decoder (Codec) implementation which can deliver high throughput performance and error correction capability for flash memory controller. In order to reduce the size of memory to store variable node LLR values, flooding schedule with column-by-column decoding architecture is exploited for the decoder. The encoder architecture provides area efficient encoding by using the specially designed H-matrix structure. The LDPC Codec IP is implemented with 700Kgates of 45nm standard CMOS technology of Samsung ASIC library and can support decoding data of 400MB/s from NAND flash without compromising the error correction capability up to raw bit-error-rate (BER) range of 2.5E-3 by hard-decision decoding mode.

Keywords

CMOS logic circuits; NAND circuits; application specific integrated circuits; codecs; decoding; error correction codes; error statistics; flash memories; parity check codes; BER range; H-matrix structure; NAND flash; Samsung ASIC library; bit-error-rate range; column-by-column decoding architecture; error correction capability; flash memory controller; hard-decision decoding LDPC codec IP design; high throughput performance; low density parity check encoder-decoder implementation; memory size reduction; size 45 nm; standard CMOS technology; temperature 700 K; variable node LLR values; Codecs; Complexity theory; Computer architecture; Decoding; Flash memory; Parity check codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6272052

Filename

6272052