A Low-Power Skew Tolerant Domino Digit Serial Multiplier

Demands for high speed low power VLSI have been pushing the development of aggressive design methodologies to reduce power consumption drastically and reduce cycle times. The objective of this research paper is to design a connection between digit-serial computing and skew tolerant domino circuit and apply it to the design of signed multipliers with reduction in number of MOS transistors used. A 16-bit signed multiplier having a digit size of 4 bits is naturally and efficiently mapped into a skew-tolerant domino implementation using 4 overlapping clock phases. To reduce the power a 14T CMOS 1-bit adder cell is used.