A very fast CMOS artificial cellular neural network

Author

Lobato-Lopez, F. ; Silva-Martínez, José ; Sánchez-Sinencio, Edgar

Author_Institution

Integrated Circuit Design Group, Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

Volume

3

fYear

1996

fDate

12-15 May 1996

Firstpage

418

Abstract

In this paper, techniques for the design of fast artificial cellular neural networks are presented. The speed limitations of the artificial Cellular Neural Networks (CNN´s) are further discussed. As a result of this study an efficient and high speed CMOS architecture is proposed. In the implementation of the building blocks, very much attention is paid to speed, power consumption and silicon area. The convergence time of the network can easily be as short as 200 nano-seconds. The current consumption of a single neuron is less than 100 μA, if all the templates are active. The network is internally re-configurable for noise reduction and edge detection. Simulated results for a 10×10 network, consisting of 1700 transistors, configured to remove noise are reported. The supply voltages are only 0-3 volts

Keywords

CMOS integrated circuits; cellular neural nets; integrated circuit design; neural chips; 0 to 3 V; 100 muA; 200 ns; artificial cellular neural network; convergence time; design; edge detection; high speed CMOS architecture; noise; power consumption; silicon area; simulation; template; Capacitors; Cellular neural networks; Convergence; Energy consumption; Equations; High speed optical techniques; Neurons; Resistors; Silicon; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541622

Filename

541622