DocumentCode
3025456
Title
Pipelined adder graph optimization for high speed multiple constant multiplication
Author
Kumm, Martin ; Zipf, Peter ; Faust, Mathias ; Chang, Chip-Hong
Author_Institution
Digital Technol. Group, Univ. of Kassel, Kassel, Germany
fYear
2012
fDate
20-23 May 2012
Firstpage
49
Lastpage
52
Abstract
This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve the PMCM problem heuristically, called RPAG, is presented. RPAG outperforms previous methods which are based on pipelining the solutions of conventional MCM algorithms. A flexible cost evaluation is used which enables the optimization for FPGA or ASIC targets on high or low abstraction levels. Results for both technologies are given and compared with the most recent methods. Even for the special case of limited AD it is shown that RPAG often produces better results compared to the prominent Hcub algorithm with minimal total AD constraint.
Keywords
adders; graph theory; optimisation; ASIC; FPGA; PMCM problem; RPAG; direct optimization; flexible cost evaluation; high speed multiple constant multiplication; limited adder depth; optimization opportunities; pipelined adder graph optimization; pipelined multiple constant multiplication; Adders; Application specific integrated circuits; Field programmable gate arrays; Optimization; Pipeline processing; Registers; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6272072
Filename
6272072
Link To Document